CMOS Power Inverter Amplifier Version 2

CMOS Power Inverter Amplifier Version 2

I decided to refine my CMOS Power Amplifier design (See CMOS Power Amp for the original version). I played with different ideas, and dropped the idea for a while. Then, tonight, I came up with this (See above schematic). While the schematic for the old version has a MOSFET buffer, I left it out of this design. I'm not that concerned with that part of the design. Several buffers can be used, and might not be needed depending on whatever preamp one uses.  

This design has several similarities with the original. The CMOS Inverter is midpoint biased and has variable feedback for gain control. It uses the same MOSFETS.

However, there are some major differences. This looks less like a digital CMOS inverter than the original. While the original has a Class A Bias, this has a Class AB bias using pots R2 and R3 to adjust the bias. The gain pot is between the input and output of the inverter stage, rather than in front. I also decided to see how this works with a 24V supply. Because the biasing pots have some effect on the feedback ratio of this amp, I added R1 to make adjustments to where one has unity gain with R6 set to 50%. The two 1uF capacitors, C1 and C3 help the signal to bypass the biasing pots to reach the gates of U1 and U2. I'll explain pots R5 and R8 in a bit.

Here is a screenshot of this design in a running simulation (paused actually) in MultiSim:

Even with double the voltage, this amp is MUCH more efficient than the original. (That being said, I did not mind that the original was inefficient. I liked having a quiet overdriven amp, and it was still kinda too loud.) This behaves like one would expect a unity gain amplifier to behave. The simulated function generator fed a 24 Vpp (12 Vp see Function Generator window) sine wave at 1 kHz. The output voltage was about 22.7Vpp and was clipping hard. With a slightly smaller input voltage, or with more feedback, the inverter put out a nice sine wave that matched the voltage of the input. The frequency response was fairly flat.

At one point, before adding R5 and R8, I noticed that I was not getting the nice sine wave I had expected, but rather a heavily rounded, clipped output like you might see from a midpoint biased CMOS inverter. This didn't make sense until I noticed that I forgot to connect C3 and C1 to the junction between R1 and R6. After connecting them, I got a slightly but abruptly clipped sine wave like in the above screen shot. It occurred to me that I could use switches to disable C3 and C1 to allow for control of the clipping characteristics of the inverter. Disabling only one could allow for some asymmetrical clipping. Then, I thought, why not use pots to fine tune the clipping characteristics. 

The following screen shot shows the results:

Notice how the oscilloscope window shows an output wave form like one might expect from a CMOS inverter. Adjusting R5 and R8 allows one to get something in between this and a hard-clipped sine wave.

R7 simulates an 8 ohm speaker load (not very well of course.) It looks like this can produce a bit more than 8 watts of clean output with an 8 ohm load. If I tweak the bias and try different speaker impedances, I might get more.

This screen shot shows a quiescent current of about 250 mA. After taking this screen shot, I got it to a bit less than 70 mA, which isn't horrible. 

Of course, this is all simulation. I haven't bread-boarded any of this yet. When I try to, I might find out that this design doesn't work the way I expect, or maybe doesn't even work at all. I can't wait to find out.
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